32-Bit Arm
®
Cortex
®
-M3 MCU
HT32F12345
USB Endpoint 0 Transfer Count Register – USBEP0TCR
This register specifies the Endpoint 0 data transfer byte count.
Offset:
0x020
Reset value: 0x0000_0000
31
Type/Reset
23
Reserved
Type/Reset
RO
15
Type/Reset
7
Reserved
Type/Reset
RW
Bits
Field
Descriptions
[22:16]
RXCNT
Reception Byte Count
The bit field contains the number of data bytes received by Endpoint 0 in the
preceding SETUP transaction.
[6:0]
TXCNT
Transmission Byte Count
The bit field contains the number of data bytes to be transmitted by Endpoint 0 in the
next IN token. If the value of this field is zero, it indicates that a zero length packet will
be sent.
Rev. 1.10
30
29
28
22
21
20
0 RO
0 RO
14
13
12
6
5
4
0 RW
0 RW
483 of 590
27
26
Reserved
19
18
RXCNT
0 RO
0 RO
0 RO
11
10
Reserved
3
2
TXCNT
0 RW
0 RW
0 RW
25
24
17
16
0 RO
0
9
8
1
0
0 RW
0
November 28, 2018
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