Holtek HT32F12345 User Manual page 448

32-Bit Arm ® Cortex ® -M3 MCU
HT32F12345
Bits Field
[11] CTSS
[10] CTSC
[9] RSADD
[8] TXC
[7] TXDE
[6] RXTOF
[5] RXDR
[4] BII
[3] FEI
[2] PEI
Rev. 1.10
Descriptions
CTS Clear-To-Send Status
0: CTS pin is inactive
1: CTS pin is active and kept at a logic low state
CTS Status Change Flag
This bit is set whenever the CTS input pin status has been changed and an Interrupt
is generated if the CTSIE = 1 in the USRIER register. Writing 1 to this bit clears the
flag.
RS485 Address Detection
0: Address is not detected
1: Address is detected
This bit is set to 1 when the receiver detects the address. An interrupt is generated if
RSADDIE = 1 in the USRIER register. Writing 1 to this bit clears the flag.
Note: This bit is only used in the RS485 mode by setting the MODE field in the
USRCR register.
Transmit Complete
0: Either transmit FIFO (TX FIFO) or transmit shift register (TSR) is not empty
1: Both the TX FIFO and TSR register are empty
An interrupt is generated if TXCIE=1 in the USRIER register. This bit is cleared by a
write to the USRDR register with new data.
Transmit Data FIFO Empty
0: TX FIFO level is higher than threshold
1: TX FIFO level is less than threshold
The TXDE bit is set when transmit FIFO level is less than the transmit FIFO
threshold level setting which is set by the TXTL field in the USRFCR register. This
bit is clear when the USRDR is written with data until TX FIFO level is higher than
threshold setting.
Receive FIFO Time-Out Flag
0: RX FIFO Time-Out Interrupt is not enabled or occurred
1: RX FIFO Time-Out Interrupt is occurred
This bit is clear when RX FIFO is empty.
Receive FIFO Ready Flag
0: RX FIFO level is less than threshold
1: RX FIFO level is higher than threshold
The RXDR bit is set when the FIFO received data amount has reached the specified
threshold level which is set by the RXTL field in the USRFCR register. This bit
is clear when the USRDR is read data until RX FIFO level is less than threshold
setting.
Break Interrupt Indicator
This bit is set to 1 whenever the received data input is held in the "spacing state"
(logic 0) for longer than a full word transmission time, which is the total time of "start
bit" + data bits + "parity" + "stop bits" duration. Writing 1 to this bit clears the flag.
Framing Error Indicator
This bit is set 1 whenever the received character does not have a valid "stop bit",
which means, the stop bit following the last data bit or parity bit is detected as logic
0. Writing 1 to this bit clears the flag.
Parity Error Indicator
This bit is set to 1 whenever the received character does not have a valid "parity bit".
Writing 1 to this bit clears the flag.
448 of 590 November 28, 2018