I 2 S Clock Divider Register - I2Scdr - Holtek HT32F12345 User Manual

32-Bit Arm ® Cortex ® -M3 MCU
HT32F12345
I 2 S Clock Divider Register – I2SCDR
This register specifics the I 2 S clock divider ratio.
Offset : 0x008
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset RW 0 RW
15
Type/Reset RW 0 RW
7
Type/Reset RW 0 RW
Bits Field
[23:16] N_DIV
[15:8] X_DIV
[7:0] Y_DIV
Rev. 1.10
30 29 28
22 21 20
0 RW 0 RW
14 13 12
0 RW 0 RW
6 5 4
0 RW 0 RW
Descriptions
N divider for BCLK
0x00: divide 1
0x01: divide 2
...
0xFF: divide 256
Note: This bit should be configured when the I
X divider for MCLK
(X = 1 ~ 255) && (X / Y ≤ 1)
Note: This bit should be configured when the I
Y divider for MCLK
(Y = 1 ~ 255) && (X / Y ≤ 1)
Note: This bit should be configured when the I
553 of 590
27 26
Reserved
19 18
N_DIV
0 RW 0 RW 0 RW
11 10
X_DIV
0 RW 0 RW 0 RW
3 2
Y_DIV
0 RW 0 RW 0 RW
2 S is disabled.
2 S is disabled.
2 S is disabled.
25 24
17 16
0 RW 0
9 8
0 RW 0
1 0
0 RW 0
November 28, 2018