System Clock (Ck_Sys) Selection; Hse Clock Monitor - Holtek HT32F12345 User Manual

32-Bit Arm ® Cortex ® -M3 MCU
HT32F12345

System Clock (CK_SYS) Selection

After the system reset occurs, the high speed internal RC oscillator HSI is selected as the system
clock (CK_SYS). The CK_SYS may come from the HSI, HSE, LSE, LSI or PLL output clock and
it can be switched from one clock source to another via the System Clock Switch bits (SW) in the
Global Clock Control Register (GCCR). The system will still run under the original clock until the
destination clock gets ready when the SW value is changed. The corresponding clock ready status
bits in the Global Clock Status Register (GCSR) will indicate whether the selected clock is ready to
use or not. The CKCU also contains the clock source status bits in the Clock Source Status Register
CKST to indicate which clock is currently used as system clock. If a clock source or the PLL output
clock is used as system clock, it is not possible to stop it. More detail about function of clock enable
is described in the following.
▄
If any event in the following occurs, the HSI will be enabled.
● Enable PLL and configure its source clock to HSI. (PLLEN, PLLSRC)
● Enable Clock monitor. (CKMEN)
● Configure clock switch register to HSI. (SW)
● Configure HSI enable register to 1. (HSIEN)
▄
If any event in the following occurs, the HSE will be enabled.
● Enable PLL and configure its source clock to HSE. (PLLEN, PLLSRC)
● Configure clock switch register to HSE. (SW)
● Configure HSE enable register to 1. (HSEEN)
● If any event in the following occurs, the PLL will be enabled.
● Enable USB Enable register. (USBEN)
● Configure clock switch register to PLL. (SW)
● Configure PLL enable register to 1. (PLLEN)
The system clock selection Programming guide is listed in the following.
▄
Enable any source clock which will become system clock or PLL input clock.
▄
Configuring the PLLSRC register after the ready flags of both HSI and HSE are asserted.
▄
Configuring the SW register to change the system clock source will occur after the corresponding
ready flag of the clock source is asserted. Note that the system clock will be forced to HSI if the
clock monitor is enabled and the PLL output or HSE clock configured as system clock is stuck at
0/1.

HSE Clock Monitor

The HSE clock monitor function is enabled by the HSE Clock Monitor Enable bit CKMEN in
the Global Clock Control Register (GCCR). This function should be enabled after the HSE start-
up delay and be disabled when the HSE oscillator is stopped. Once the HSE failure is detected,
the HSE will automatically be disabled. The HSE Clock Stuck Flag CKSF in the Global Clock
Interrupt Register, GCIR, will be set and the HSE failure event will be generated if the Clock Fail
Interrupt Enable bit CKSIE in the GCIR register is set. This failure interrupt is connected to the
Non-Maskable Interrupt NMI. When the HSE oscillator failure occurs, the HSE will be turned off
and the system clock will be switched to the HSI automatically by the hardware. If the HSE is used
as the clock input of the PLL circuit whose output is used as the system clock, the PLL circuit will
also be turned off as well as the HSE when the failure happens.
Rev. 1.10 91 of 590 November 28, 2018