I 2 S Fifo Control Register - I2Sfcr - Holtek HT32F12345 User Manual

32-Bit Arm ® Cortex ® -M3 MCU
HT32F12345
I 2 S FIFO Control Register – I2SFCR
This register contains the related I
Offset : 0x014
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
Type/Reset
7
Type/Reset RW 0 RW
Bits Field
[9] RXFRST
[8] TXFRST
[7:4] RXFTLS
[3:0] TXFTLS
Rev. 1.10
2 S FIFO control bits.
30 29 28
22 21 20
14 13 12
Reserved
6 5 4
RXFTLS
0 RW 0 RW
Descriptions
RX FIFO Reset
Set this bit to reset the RX FIFO.
TX FIFO Reset
Set this bit to reset the TX FIFO.
RX FIFO Trigger Level Select
0000: Trigger level is 0
0001: Trigger level is 1
...
0111: Trigger level is 7
1xxx: Trigger level is 8
When the data contained in the RX FIFO is equal to or greater than the level
defined by the RXFTLS field, the RXFTL flag will be set.
TX FIFO Trigger Level Select
0000: Trigger level is 0
0001: Trigger level is 1
...
0111: Trigger level is 7
1xxx: Trigger level is 8
When the data contained in the TX FIFO is equal to or less than the level defined
by the TXFTLS field, the TXFTL flag will be set.
555 of 590
27 26
Reserved
19 18
Reserved
11 10
RW
3 2
0 RW 0 RW 0 RW
25 24
17 16
9 8
RXFRST TXFRST
0 RW 0
1 0
TXFTLS
0 RW 0
November 28, 2018