Holtek HT32F12345 User Manual page 264

32-Bit Arm ® Cortex ® -M3 MCU
HT32F12345
Bits Field
[4] CH0PRE
[3] REF0CE
[8][2:0] CH0OM[3:0] Channel 0 Output Mode Setting
Rev. 1.10
Descriptions
Channel 0 Capture / Compare Register (CH0CCR) Preload Enable
0: CH0CCR preload function is disabled
The CH0CCR register can be immediately assigned a new value when
the CH0PRE bit is cleared to 0 and the updated CH0CCR value is used
immediately.
1: CH0CCR preload function is enabled
The new CH0CCR value will not be transferred to its shadow register until the
update event occurs.
Channel 0 Reference Output Clear Enable
0: CH0OREF performed normally and is not affected by the ETIF signal
1: CH0OREF is forced to 0 on the high level of the ETIF signal derived from the
GTn_ETI pin
These bits define the functional types of the output reference signal CH0OREF.
0000: No Change
0001: Output 0 on compare match
0010: Output 1 on compare match
0011: Output toggles on compare match
0100: Force inactive – CH0OREF is forced to 0
0101: Force active – CH0OREF is forced to 1
0110: PWM mode 1
- During up-counting, channel 0 has an active level when CNTR <
CH0CCR or otherwise has an inactive level.
- During down-counting, channel 0 has an inactive level when CNTR >
CH0CCR or otherwise has an active level.
0111: PWM mode 2
- During up-counting, channel 0 is has an inactive level when CNTR <
CH0CCR or otherwise has an active level.
- During down-counting, channel 0 has an active level when CNTR >
CH0CCR or otherwise has an inactive level.
1110: Asymmetric PWM mode 1
- During up-counting, channel 0 has an active level when CNTR <
CH0CCR or otherwise has an inactive level.
- During down-counting, channel 0 has an inactive level when CNTR >
CH0ACR or otherwise has an active level.
1111: Asymmetric PWM mode 2
- During up-counting, channel 0 has an inactive level when CNTR <
CH0CCR or otherwise has an active level.
- During down-counting, channel 0 has an active level when CNTR >
CH0ACR or otherwise has an inactive level
Note: When channel 0 is used as asymmetric PWM output mode, the Counter Mode
Selection bit in Counter Configuration Register must be configured as center
align mode (CMSEL = 01 / 02 / 03).
264 of 590 November 28, 2018