Register Descriptions; I 2 S Control Register - I2Scr - Holtek HT32F12345 User Manual

32-Bit Arm ® Cortex ® -M3 MCU
HT32F12345

Register Descriptions

I 2 S Control Register – I2SCR
This register specifies the corresponding I
Offset: 0x000
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
CLKDEN
Type/Reset RW 0 RW
7
Type/Reset RW 0 RW
Bits Field
[19] MCKINV
[18] BCKINV
[17] RCSEL
[16] RCEN
[15] CLKDEN
[14] RXDMAEN
[13] TXDMAEN
[12] TXMUTE
Rev. 1.10
2 S function enable control.
30 29
22 21
Reserved
14 13
RXDMAEN TXDMAEN TXMUTE CHANNEL
0 RW 0 RW
6 5
FORMAT SMPSIZE
0 RW 0 RW
Descriptions
MCLK Inverse Enable
0: Disable
1: Enable
BCLK Inverse Enable
0: Disable
1: Enable
Rate Control Select (master only)
0: Slower
1: Faster
Rate Control Enable (master only)
0: Disable
1: Enable
Clock Divider Enable (master only)
0: Disable
1: Enable
The clock divider can be used to generate the MCLK and BCLK clock of the I
interface for master mode.
RX PDMA Request Enable
0: Disable
1: Enable
TX PDMA Request Enable
0: Disable
1: Enable
TX Mute Enable
0: Disable
1: Enable
550 of 590
28 27 26
Reserved
20 19 18
MCKINV BCKINV
RW 0 RW
12 11 10
REPEAT
0 RW 0 RW
4 3 2
MS RXEN
0 RW 0 RW
25 24
17 16
RCSEL RCEN
0 RW 0 RW 0
9 8
MCLKEN BITEXT
0 RW 0 RW 0
1 0
TXEN I2SEN
0 RW 0 RW 0
2 S
November 28, 2018