Pll Configuration Register - Pllcfgr - Holtek HT32F12345 User Manual

32-Bit Arm ® Cortex ® -M3 MCU
HT32F12345
PLL Configuration Register – PLLCFGR
This register specifies the PLL configurations.
Offset: 0x018
Reset value: 0x0000_0000
31
Type/Reset
23
PFBD
Type/Reset RW 0 RW
15
Type/Reset
7
USBPFBD
Type/Reset RW 0 RW
Bits Field
[27:23] PFBD
[22:21] POTD
[10:7] USBPFBD
[6:5] USBPOTD
Rev. 1.10
30 29 28
Reserved
22 21 20
POTD
0 RW 0
14 13 12
Reserved
6 5 4
USBPOTD
0 RW 0
Descriptions
PLL VCO Output Clock Feedback Divider (B4 ~ B0)
Feedback Divider divides the output clock from VCO of PLL.
PLL Output Clock Divider (S1 ~ S0)
USB PLL VCO Output Clock Feedback Divider (B3 ~ B0)
Feedback Divider divides the output clock from VCO of PLL.
USB PLL Output Clock Divider (S1 ~ S0)
99 of 590
27 26
PFBD
RW 0 RW 0 RW
19 18
Reserved
11 10
USBPFBD
RW 0 RW
3 2
Reserved
25 24
0 RW 0
17 16
9 8
0 RW 0
1 0
November 28, 2018