32-Bit Arm
®
Cortex
®
-M3 MCU
HT32F12345
13
Comparator (CMP)
Introduction
Two general purpose comparators, CMP, are implemented within the devices. They can be
configured either as standalone comparators or combined with the different kinds of peripheral IP.
Each comparator is capable of asserting interrupts to the NVIC or wake up the CPU from the Sleep
or Deep Sleep mode through EXTI wakeup event management unit.
Comparator Analog IP
CP
CN
Reserved
Reserved
CVREN
V
DDA
0
6-Bit
V
REF+
1
Scaler
V
SSA
CVRSS
CVRVAL[5:0]
Figure 34. CMP with Digital I/O Block Diagram
Features
▄
Rail-to-rail comparator
▄
Each comparator has configurable negative inputs used for flexible voltage selection
●
Dedicated I/O pin
●
Internal voltage reference provided by 6-bit scaler
▄
Programmable hysteresis
▄
Programming speed and consumption
▄
Comparator output can be output to I/O or to multiple timer or ADC trigger inputs
▄
Programmable internal voltage reference provided by 6-bit scaler
▄
Comparator has interrupt generation capability with wakeup from Sleep or Deep Sleep modes
through the EXTI controller
Rev. 1.10
Programmable
Hysteresis
CMPEN
Programmable
Response Time
CMPINSEL[1:0]
CVREF
CVROE
V
Domain
DDA
215 of 590
0
CMPOUT
1
CMPSTS
Sync
CMPPOL
SYNCSEL
HCLK
Control &
Interrupt
Generator
V
Domain
CORE
AFIO
GPIO
0
COUT
1
CMP Status
& Interrupt
Reguest
ADC
MCTM
GPTM
To EXTI
Wakeup
Event
Management
November 28, 2018
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