32-Bit Arm
®
Cortex
®
-M3 MCU
HT32F12345
Bits
Field
[31:0]
PCDVn[1:0]
Port C Lock Register – PCLOCKR
This register specifies the GPIO Port C lock configuration.
Offset:
0x018
Reset value: 0x0000_0000
31
Type/Reset
RW
0 RW
23
Type/Reset
RW
0 RW
15
Type/Reset
RW
0 RW
7
Type/Reset
RW
0 RW
Bits
Field
[31:16]
PCLKEY
Rev. 1.10
Descriptions
GPIO Port C pin n Output Current Drive Selection Control Bits (n = 0 ~ 15)
00: 4 mA source / sink current
01: 8 mA source / sink current
10: 12 mA source / sink current
11: 16 mA source / sink current
Becuase the PC13 ~ 15 are located at the Backup Domain. Therefore only the sink
current capability can be set with PCDV [0] bit and don't care the PCDV [1] bit.
x0: 4 mA sink current
x1: 8 mA sink current
For the soruce current of this pins are always limited at 1 mA.
30
29
28
0 RW
0 RW
22
21
20
0 RW
0 RW
14
13
12
0 RW
0 RW
6
5
0 RW
0 RW
Descriptions
GPIO Port C lock Key
0x5FA0: Port C Lock function is enable
Others: Port C Lock function is disable
To lock the Port C function, a value 0x5FA0 should be written into the PCLKEY field
in this register. To execute a successful write operation on this lock register, the
value written into the PCLKEY field must be 0x5FA0. If the value written into this
field is not equal to 0x5FA0, any write operations on the PCLOCKR register will be
aborted. The result of a read operation on the PCLKEY field returns the GPIO Port
C Lock Status which indicates whether the GPIO Port C is locked or not. If the read
value of the PCLKEY field is 0, this indicates that the GPIO Port C Lock function is
disabled. Otherwise, it indicates that the GPIO Port C Lock function is enabled as
the read value is equal to 1.
146 of 590
27
26
PCLKEY
0 RW
0 RW
19
18
PCLKEY
0 RW
0 RW
11
10
PCLOCK
0 RW
0 RW
4
3
2
PCLOCK
0 RW
0 RW
25
24
0 RW
0 RW
0
17
16
0 RW
0 RW
0
9
8
0 RW
0 RW
0
1
0
0 RW
0 RW
0
November 28, 2018
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