Sd Clock; Figure 210. Normal Speed Timing; Figure 211. High Speed Timing; Figure 212. Sd_Clk Duty Cycle - Holtek HT32F12345 User Manual

32-Bit Arm ® Cortex ® -M3 MCU
HT32F12345

SD Clock

The SD_CLK is a clock driven by the SDIO controller and transmitted to the card. When the CK_
AHB is operating at 96 MHz, the maximum SD_CLK frequency is 48 MHz in the high speed
mode and 24 MHz in the normal speed mode. In the normal speed mode, the CMD and DAT lines
are changed at the SD_CLK falling edge and latched at the SD_CLK rising edge. In the high speed
mode, the CMD and DAT lines are changed and latched at the SD_CLK rising edge.

Figure 210. Normal Speed Timing

Figure 211. High Speed Timing

Figure 212. SD_CLK Duty Cycle

Rev. 1.10
SD_CLK = CK_AHB / (CLKPRE + 1), CLKPRE = 0 ~ 255
SD_CLK
CMD, DAT
(output)
SD_CLK
t
OV(HS)
CMD, DAT
(output)
566 of 590
t t
OV(SD) OH(SD)
t
OH(HS)
CK_AHB
SD_CLK=CK_AHB/2
SD_CLK=CK_AHB/3, higher duty
SD_CLK=CK_AHB/3, lower duty
November 28, 2018