Channel 3 Input Configuration Register - Ch3Icfr - Holtek HT32F12345 User Manual

32-Bit Arm ® Cortex ® -M3 MCU
HT32F12345
Channel 3 Input Configuration Register – CH3ICFR
This register specifies the channel 3 input mode configuration.
Offset: 0x02C
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
Type/Reset
7
Type/Reset
Bits Field
[19:18] CH3PSC
[17:16] CH3CCS
Rev. 1.10
30 29 28
22 21 20
Reserved
14 13 12
6 5
Reserved
Descriptions
Channel 3 Capture Input Source Prescaler Setting
These bits define the effective events of the channel 3 capture input. Note that the
prescaler is reset once the Channel 3 Capture / Compare Enable bit, CH3E, in the
Channel Control register named CHCTR is cleared to 0.
00: No prescaler, channel 3 capture input signal is chosen for each active event
01: Channel 3 Capture input signal is chosen for every 2 events
10: Channel 3 Capture input signal is chosen for every 4 events
11: Channel 3 Capture input signal is chosen for every 8 events
Channel 3 Capture / Compare Selection
00: Channel 3 is configured as an output
01: Channel 3 is configured as an input derived from the TI3 signal
10: Channel 3 is configured as an input derived from the TI2 signal
11: Channel 3 is configured as an input which comes from the TRCED signal
derived from the Trigger Controller
Note: The CH3CCS field can be accessed only when the CH3E bit is cleared to 0.
338 of 590
27 26
Reserved
19 18
CH3PSC
RW 0 RW
11 10
Reserved
4 3 2
RW 0 RW
25 24
17 16
CH3CCS
0 RW 0 RW 0
9 8
1 0
TI3F
0 RW 0 RW 0
November 28, 2018