Register Descriptions; Pdma Channel N Control Register - Pdmachncr, N = 0 ~ 11 - Holtek HT32F12345 User Manual

32-Bit Arm ® Cortex ® -M3 MCU
HT32F12345

Register Descriptions

PDMA Channel n Control Register – PDMACHnCR, n = 0 ~ 11
This register is used to specify the PDMA channel n data transfer configuration.
Offset: 0x000 (0), 0x018 (1), 0x030 (2), 0x048 (3), 0x060 (4), 0x078 (5), 0x090 (6), 0x0A8 (7), 0x0C0 (8),
0x0D8 (9), 0x0F0 (10), 0x108 (11)
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
Type/Reset
7
SRCAMODn SRCAINCn DSTAMODn DSTAINCn
Type/Reset RW 0 RW
Bits Field
[11] AUTORLn
[10] FIXAENn
[9:8] CHnPRI
Rev. 1.10
30 29
22 21
14 13
Reserved
6 5
0 RW 0 RW
Descriptions
Channel n Auto Reload Enable Control
0: Disable Auto Reload function
1: Enable Auto Reload function
If this bit is set to 1 to enable the auto-reload function, the channel n current address
and the channel n current transfer size will be reloaded with the relevant start value
and the PDMA channel n will be activated when a transfer is complete. If this bit is
cleared to 0, the channel n current address and the channel n current transfer size
will remain unchanged and the PDMA channel n will be disabled after a transfer
completion.
Channel n Fixed Address Enable control
0: Disable fixed address function in the circular address mode
1: Enable fixed address function in the circular address mode
Note that this bit is only available when the source or destination address mode is
set to be in the circular address mode. For example, the source address mode is
set as in the linear address mode and the destination address mode is set as in the
circular mode. If this bit is set to enable the fixed address function, then the source
address mode will still be in the linear address but the destination address mode will
be in the fixed address mode instead of the circular address mode.
Channel n Priority
00: Low
01: Medium
10: High
11: Very high
The CHnPRI field is used to configure the channel priority using the application
program. If there are more than one channel which have the same software
configured priority level, the channel with the smaller channel number will have
priority to transfer one block of data after the arbitration.
503 of 590
28 27 26
Reserved
20 19 18
Reserved
12 11 10
AUTORLn FIXAENn
RW 0 RW
4 3 2
DWIDTHn SWTRIGn
0 RW 0 RW
25 24
17 16
9 8
CHnPRI
0 RW 0 RW 0
1 0
CHnEN
0 RW 0 RW 0
November 28, 2018