32-Bit Arm
®
Cortex
®
-M3 MCU
HT32F12345
28
SDIO Host Controller (SDIO)
Introduction
The SDIO Host Controller supports Multi-Media Cards (MMC), the SD Memory Cards and SD
I/O cards. The SDIO communication is based on an advanced 6-pin interface composed of clock,
command and 4 × data lines.
Figure 208. SDIO Bus Topology
Features
▄
Supports two different data bus modes: 1-bit (default) and 4-bit
▄
Supports two different speed modes: Normal speed (default) and High speed
▄
SD clock frequency of up to system frequency
▄
SPI mode and MMC stream mode not supported
Functional Description
The SDIO includes a command register, argument register, response registers, data buffer, timeout
counter and error detection logic. The SDIO supports single block and multi-block data transfers
and is compatible with the PDMA, minimizing processor intervention for large data transfers.
DMA request
Figure 209. SDIO Block Diagram
Rev. 1.10
SDIO
Host
SD_CLK
SD_CLK
V
V
DD
DD
V
V
SS
SS
DAT0~DAT3
DAT0~DAT3,CMD
CMD
CLK:
Host to card clock signal
CMD:
Bidirectional Command/Response signal
DAT0~DAT3:
4 Bidirectional data signals.
AHB bus
Registers
CK_AHB
FIFO
Interrupt
SDIO
565 of 590
Device
SD Memory Card
or
MMC Memory Card
or
SD I/O Card
Command
SD_CLK
Path
SD_CMD
Data Path
SD_DAT[3:0]
November 28, 2018
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