Spi Serial Frame Format; Table 49. Spi Interface Format Setup; Figure 141. Spi Single Byte Transfer Timing Diagram - Cpol = 0, Cpha = 0 - Holtek HT32F12345 User Manual

32-Bit Arm ® Cortex ® -M3 MCU
HT32F12345

SPI Serial Frame Format

The SPI interface format is base on the Clock Polarity, CPOL, and the Clock Phase, CPHA,
configurations.
▄
Clock Polarity Bit – CPOL
When the Clock Polarity bit is cleared to 0, the SCK line idle state is LOW. When the Clock
Polarity bit is set to 1, the SCK line idle state is HIGH.
▄
Clock Phase Bit – CPHA
When the Clock Phase bit is cleared to 0, the data is sampled on the first SCK clock transition.
When the Clock Phase bit is set to1, the data is sampled on the second SCK clock transition.
There are four formats contained in the SPI interface. Table 49 shows how to configure these
formats by setting the FORMAT field in the SPICR1 register.

Table 49. SPI Interface Format Setup

CPOL = 0, CPHA = 0
In this format, the received data is sampled on the SCK line rising edge while the transmitted data
is changed on the SCK line falling edge. In the master mode, the first bit is driven when data is
written into the SPIDR Register. In the slave mode, the first bit is driven when the SEL signal goes
to an active level. Figure 141 shows the single byte data transfer timing of this format.
SEL (SELAP=0)
SEL (SELAP=1)
½ SCK
SCK
MOSI TX[7]
MISO RX[7]
data sampled
Figure 141. SPI Single Byte Transfer Timing Diagram – CPOL = 0, CPHA = 0
Rev. 1.10
FORMAT CPOL
[2:0]
001
010
110
101
Others
TX[6] TX[5] TX[4]
RX[6]
RX[5] RX[4]
413 of 590
CPHA
0 0
0 1
1 0
1 1
Reserved
TX[3] TX[2] TX[1]
RX[3] RX[2] RX[1]
TX[0]
RX[0]
November 28, 2018