32-Bit Arm
®
Cortex
®
-M3 MCU
HT32F12345
Bits
Field
[11]
CHANNEL
[10]
REPEAT
[9]
MCLKEN
[8]
BITEXT
[7:6]
FORMAT
[5:4]
SMPSIZE
[3]
MS
[2]
RXEN
[1]
TXEN
[0]
I2SEN
Rev. 1.10
Descriptions
Stereo or Mono
0: Stereo
1: Mono
Note: This bit should be configured when I
Repeat Mode
0: Disable
1: Enable
This mode is for I
2
S-justified stereo configuration only, transmitting the mono data
on both channels and receiving just the left channel data and ignoring the right.
Enabling the repeat mode will reset the CHANNEL bit automatically.
Note: This bit should be configured when the I
MCLK Output Enable (master only)
0: Disable
1: Enable
Note: This bit should be configured when the I
32-bit Channel Enable
0: Disable
1: Enable
Setting this bit will force the channel size to 32-bits. If the sample size is 8/16/24-
bit, the remaining bits will be forced to 0 in the TX and ignored in the RX.
Note: This bit should be configured when the I
Data Format
00: I
2
S-justified
01: Left-justified
10: Right-justified
11: reserved
Note: This bit should be configured when the I
Sample Size
00: 8-bit
01: 16-bit
10: 24-bit
11: 32-bit
Note: This bit should be configured when the I
Master or Slave Mode
0: Master
1: Slave
Note: This bit should be configured when the I
RX Enable
0: Disable
1: Enable
TX Enable
0: Disable
1: Enable
I
S Enable
2
0: Disable
1: Enable
551 of 590
2
S is disabled.
S is disabled.
2
2
S is disabled.
2
S is disabled.
2
S is disabled.
2
S is disabled.
2
S is disabled.
November 28, 2018
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