Holtek HT32F12345 User Manual page 423

32-Bit Arm ® Cortex ® -M3 MCU
HT32F12345
Bits Field
[14] MODE
[13] SELM
[12] FIRSTBIT
[11] SELAP
[10:8] FORMAT
[3:0] DFL
Rev. 1.10
Descriptions
Master or Slave Mode
0: Slave mode
1: Master mode
Slave Select Mode
0: SEL signal is controlled by software – asserted or de-asserted by the SSELC
bit
1: SEL signal is controlled by hardware – generated automatically by the SPI
hardware
Note that SELM bit is available for master mode only – MODE = 1
LSB or MSB Transmitted First
0: MSB transmitted first
1: LSB transmitted first
Slave Select Active Polarity
0: SEL signal is active low
1: SEL signal is active high
SPI Data Transfer Format
These three bits are used to determine the data transfer format of the SPI interface
FORMAT [2:0]
001
010
110
101
Others
CPOL: Clock Polarity
0: SCK Idle state is low
1: SCK Idle state is high
CPHA: Clock Phase
0: Data is captured on the first SCK clock edge
1: Data is captured on the second SCK clock edge
Data Frame Length
Selects the data transfer frame from 1 bit to 16 bits.
0x1: 1 bit
0x2: 2 bits
...
0xF: 15 bits
0x0: 16 bits
423 of 590
CPOL CPHA
0 0
0 1
1 0
1 1
Reserved
November 28, 2018