32-Bit Arm
®
Cortex
®
-M3 MCU
HT32F12345
TI0SRC
GTn_CH0
TI0XOR
GTn_CH1
XOR
GTn_CH2
TI0
TI0FP
Filter
fsampling
TI0F
TI1
GTn_CH1
TI1FP
Filter
fsampling
TI1F
Figure 62. Input Stage and Quadrature Decoder Block Diagram
Table 32. Counting Direction and Encoding Signals
Counting mode
Counting on TI0 only
(SMSEL = 0x01)
Counting on TI1 only
(SMSEL = 0x02)
Counting on TI0 and TI1
(SMSEL = 0x03)
Note: "—" → means "no counting", "X" → impossible
Rev. 1.10
TRCED
f
CLKIN
Edge
Detection
Edge
Detection
f
CLKIN
TI0S0
TI0FN
CH0P
TI1S0
TI0S1
CH1P
TI1S1
TI1FN
TI0S0ED
Level
Rising
TI1S1 = High
Down
TI1S1 = Low
Up
TI0S0 = High
—
TI0S0 = Low
—
TI1S1 = High
Down
TI1S1 = Low
Up
TI0S0 = High
X
TI0S0 = Low
X
241 of 590
CH0CCS
TI0S0ED
Edge
Detection
TI1S0ED
Edge
Detection
TI0S1ED
Edge
Detection
TI1S1ED
Edge
Detection
CH1CCS
TI0S0
TI1S1
TI0S0ED
Quadrature
TI1S0ED
Decoder
TI0S1ED
TI1S1ED
SMSEL
TI0S0
Falling
Rising
Up
Down
—
—
Down
Up
Down
X
X
Down
TI0BED
CH0PSC
CH0PRESCALER
CH0CAP Event
CH0PSC
CH1PSC
CH1PRESCALER
CH1CAP Event
CH1PSC
TI1S1
Falling
—
—
—
—
Up
Down
Up
X
X
X
X
Up
Down
Up
November 28, 2018
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