32-Bit Arm
®
Cortex
®
-M3 MCU
HT32F12345
Figure 219. Usual Data Format for Wide Bus – DAT0~DAT3 used
The wide width data is shifted starting from the MSB bit. When the wide bus option is used, the
data is transmitted 4 bits at a time. The start, end and CRC bits are transmitted for every one of
the DAT lines. The CRC bits are calculated and checked for each DAT line individually. The CRC
status response and the Busy indication will be sent from the SD device to the host on DAT0 only.
b511
Ex. SD Status
Wide Width Data
Figure 220. Wide Width Data Format for Standard Bus – only DAT0 used
DAT3
DAT2
DAT1
DAT0
Figure 221. Wide Width Data Format for Wide Bus – DAT0 ~ DAT3 used
Rev. 1.10
Start bit
1st Byte
2nd Byte
3rd Byte
Data
Data
Data
DAT3
0
b7 b3 b7 b3 b7 b3
DAT2
0
b6 b2 b6 b2 b6 b2
DAT1
0
b5 b1 b5 b1 b5 b1
DAT0
0
b4 b0 b4 b0 b4 b0
Start bit
b0
DAT0
0
b511 b510 b509
Data Packet Format for Standard Bus (only DAT0 used)
Start bit
0
b511 b507 b503
b499
0
b510 b506 b502
b498
0
b509 b505 b501
b497
0
b508 b504 b500
b496
Data Packet Format for Wide Bus (all four lines used)
570 of 590
n th Byte
End bit
Data
...
b7 b3
CRC
1
...
b6 b2
CRC
1
...
b5 b1
CRC
1
...
b4 b0
CRC
1
...
b508
b1
b0
CRC
End bit
...
b7
b3
CRC
1
...
b6
b2
CRC
1
...
b5
b1
CRC
1
...
b4
b0
CRC
1
End bit
1
November 28, 2018
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