Holtek HT32F12345 User Manual page 8

32-Bit Arm ® Cortex ® -M3 MCU
HT32F12345
14 General-Purpose Timer (GPTM) ...................................................................... 224
Introduction ........................................................................................................................ 224
Features ............................................................................................................................. 225
Functional Descriptions ..................................................................................................... 225
Counter Mode ............................................................................................................................... 225
Clock Controller ............................................................................................................................ 227
Trigger Controller .......................................................................................................................... 228
Slave Controller ............................................................................................................................ 230
Master Controller .......................................................................................................................... 232
Channel Controller ........................................................................................................................ 232
Input Stage ................................................................................................................................... 235
Output Stage ................................................................................................................................. 236
Update Management .................................................................................................................... 240
Quadrature Decoder ..................................................................................................................... 240
Digital Filter ................................................................................................................................... 242
Clearing the CHxOREF when ETIF is high ................................................................................... 243
Single Pulse Mode ........................................................................................................................ 244
Asymmetric PWM Mode ............................................................................................................... 246
Time Interconnection .................................................................................................................... 246
Trigger ADC Start.......................................................................................................................... 249
PDMA Request ............................................................................................................................. 249
Register Map ..................................................................................................................... 250
Register Descriptions ......................................................................................................... 251
Timer Counter Configuration Register - CNTCFR ....................................................................... 251
Timer Mode Configuration Register - MDCFR ............................................................................. 252
Timer Trigger Configuration Register - TRCFR ............................................................................ 255
Timer Counter Register - CTR ..................................................................................................... 257
Channel 0 Input Configuration Register - CH0ICFR .................................................................... 258
Channel 1 Input Configuration Register - CH1ICFR .................................................................... 259
Channel 2 Input Configuration Register - CH2ICFR .................................................................... 260
Channel 3 Input Configuration Register - CH3ICFR .................................................................... 262
Channel 0 Output Configuration Register - CH0OCFR ............................................................... 263
Channel 1 Output Configuration Register - CH1OCFR ............................................................... 265
Channel 2 Output Configuration Register - CH2OCFR ............................................................... 266
Channel 3 Output Configuration Register - CH3OCFR ............................................................... 268
Channel Control Register - CHCTR ............................................................................................. 270
Channel Polarity Configuration Register - CHPOLR .................................................................... 271
Timer PDMA/Interrupt Control Register - DICTR ......................................................................... 272
Timer Event Generator Register - EVGR ..................................................................................... 273
Timer Interrupt Status Register - INTSR ...................................................................................... 275
Timer Counter Register - CNTR................................................................................................... 277
Timer Prescaler Register - PSCR ................................................................................................ 277
Timer Counter Reload Register - CRR ........................................................................................ 278
Channel 0 Capture / Compare Register - CH0CCR .................................................................... 278
Rev. 1.10 8 of 590 November 28, 2018