Channel 3 Output Configuration Register - Ch3Ocfr - Holtek HT32F12345 User Manual

32-Bit Arm ® Cortex ® -M3 MCU
HT32F12345
Channel 3 Output Configuration Register – CH3OCFR
This register specifies the channel 3 output mode configuration.
Offset: 0x04C
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
Type/Reset
7
Reserved
Type/Reset
Bits Field
[5] CH3IMAE
[4] CH3PRE
[3] REF3CE
Rev. 1.10
30 29 28
22 21 20
14 13 12
Reserved
6 5 4
CH3IMAE CH3PRE
RW 0 RW
Descriptions
Channel 3 Immediate Active Enable
0: No action
1: Single pulse Immediate Active Mode enabled
The CH3OREF will be forced to the compare matched level immediately after an
available trigger event occurs irrespective of the result of the comparison between
the CNTR and the CH3CCR values.
The effective duration ends automatically at the next overflow or underflow event.
Note: The CH3IMAE bit is available only if channel 3 is configured to be operated in
PWM mode 1 or PWM mode 2.
Channel 3 Capture / Compare Register (CH3CCR) Preload Enable
0: CH3CCR preload function is disabled.
The CH3CCR register can be immediately assigned a new value when
the CH3PRE bit is cleared to 0 and the updated CH3CCR value is used
immediately.
1: CH3CCR preload function is enabled
The new CH3CCR value will not be transferred to its shadow register until an
update event 1 occurs.
Channel 3 Reference Output Clear Enable
0: CH3OREF operates normally and is not affected by the ETIF signal
1: CH3OREF is forced to 0 during the high level of the ETIF signal derived from
the MTn_ETI pin
344 of 590
27 26
Reserved
19 18
Reserved
11 10
3 2
REF3CE CH3OM[2:0]
0 RW 0 RW 0 RW
25 24
17 16
9 8
CH3OM[3]
RW 0
1 0
0 RW 0
November 28, 2018