Figure 154. Usart Rts Flow Control; Figure 155. Usart Cts Flow Control - Holtek HT32F12345 User Manual

32-Bit Arm ® Cortex ® -M3 MCU
HT32F12345
RTS Flow Control
In the RTS flow control, the USART RTS pin is active with a logic low state when the receive data
register is empty. It means that the receiver is ready to receive a new data. When the RX FIFO
reaches the trigger level which is specified by configuring the RXTL field in the USRFCR register,
the USART RTS pin is inactive with a logic high state. Figure 154 shows the example of RTS flow
control.
Start Bit
Bit 0 Bit 1 Bit 2 Bit 3
RTS
RXFS[3:0] 3

Figure 154. USART RTS Flow Control

CTS Flow Control
If the hard flow control function is enabled, the URTXEN bit in the USRCR register is controlled
by the USART CTS input signal. If the USART CTS pin is forced to a logic low state, the
URTXEN bit will automatically be set to 1 to enable the data transmission. However, if the USART
CTS pin is forced to a logic high state, the URTXEN bit will be cleared to 0 and then the data
transmission will also be disabled.
When the USART CTS pin is forced to a logic high state during a data transmission period, the
current data transmission will be continued until the stop bit is completed. The Figure 155 shows
an example of communication with CTS flow control.
Start Bit
Bit 0 Bit 1 Bit 2 Bit 3 Bit 4
CTS
TXFS[3:0] 4

Figure 155. USART CTS Flow Control

Rev. 1.10
Parity Bit
Bit 4 Bit N Stop Bit
Idle
N=6~8
4
Reach the RX trigger level
Read data until RX FIFO is empty
RFTL[2:0] = 0x10
Parity Bit
Start Bit
Stop Bit
Bit N Idle
N=6~8
435 of 590
Start Bit
Bit 0 Bit 1 Bit 2 Bit 3
0
Bit 0 Bit 1 Bit 2 Bit 3 Bit 4
3
Parity Bit
Stop Bit
Bit 4 Bit N
N=6~8
1
Parity Bit Start Bit
Stop
Bit N Bit 0
Bit
N=6~8
2
November 28, 2018