32-Bit Arm
®
Cortex
®
-M3 MCU
HT32F12345
Slave Controller
The MCTM can be synchronised with an internal / external trigger in several modes including the
Restart mode, the Pause mode and the Trigger mode which are selected by the SMSEL field in the
MDCFR register. The trigger input of these modes comes from the STI signal which is selected by
the TRSEL field in the TRCFR register. The operation modes in the Slave Controller are described
in the accompanying sections.
Trigger Controller
Figure 84. Slave Controller Diagram
Restart Mode
The counter and its prescaler can be reinitialised in response to an STI signal rising edge. If
the UEV1DIS bit is set to 1 to disable the update event, then no update event will be generated,
however the counter and prescaler are still reinitialised when an STI rising edge occurs. If the
UEV1DIS bit in the CNTCFR register is cleared to enable the update event, then an update event
will be generated together with the STI rising edge and all the preloaded registers will be updated.
Timer Counter Reload Register CRR = 32
STI source signal
(polarity=0)
STI source signal
(polarity=1)
CK_CNT
UEV1G bit
(reset counter)
(Up-counting)
(Down-counting)
Figure 85. MCTM in Restart Mode
Rev. 1.10
STI
Controller
STI
CNTR
27
28
29
CNTR
27
26
25
TEVIF
298 of 590
Trigger Event
Slave
Reset/Stop/Start Counter
SMSEL
Restart/Pause/Trigger Mode
Sync.
Trigger Event
30
31
0
1
24
23
32
31
2
30
November 28, 2018
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