Ahb Transaction Width Conversion; Table 66. Ebi Maps Ahb Transactions Width To External Device Transactions; Figure 186. Ebi De-Asserts An Idle Cycle Between Transactions In The Same Bank (Noidle = 1) - Holtek HT32F12345 User Manual

32-Bit Arm ® Cortex ® -M3 MCU
HT32F12345
RDSETUP
(0, 1, 2, ...)
EBI_A[N:0]
EBI_AD[15:0]
EBI_CSn
EBI_OE

Figure 186. EBI De-asserts an IDLE Cycle between Transactions in the Same Bank (NOIDLE = 1)

AHB Transaction Width Conversion

The mapping of AHB transactions to an external device depends on the data width of the external
device and whether the byte lanes of the external device are supported or not. The Table 66 shows
the EBI mapping of AHB transactions to external device transactions. The EBI will automatically
translate the different AHB transaction width to external device transactions which matches the
external bus capabilities of the device.
▄
If the AHB master (CPU or PDMA) transaction width is larger than the external bus transaction
width. The EBI will split and translate the AHB transaction into consecutive multiple external
transactions which have consecutively incrementing the address and start with the least significant
data from AHB transaction.
▄
If the AHB master (CPU or PDMA) transaction width is smaller than the external bus transaction
width. The EBI behavior depends on whether the byte lanes are available or not. Reads either use
byte lanes to select the required data when it is available, or read according to the full data bus
width of the external device and ignore the superfluous data when a byte lane is not available.
Writes either uses a byte lane to select the required data when it is available, or EBI automatically
perform a read-modify-write sequence when a byte lane is not available.

Table 66. EBI Maps AHB Transactions Width to External Device Transactions

AHB
Transaction
8-bit read
16-bit read
32-bit read
8-bit write
16-bit write
32-bit write
Rev. 1.10
RDSTRB RDHOLD
(1, 2, 3, ...) (0, 1, 2, ...)
ADDR0
DATA0
16-bit External
8-bit External
Device Transaction
Device Transaction
(with byte lanes)
1 × 8-bit read
(using byte lane)
2 × 8-bit read
4 × 8-bit read
1 × 8-bit write
(using byte lane)
2 × 8-bit write
4 × 8-bit write
524 of 590
RDSETUP RDSTRB
(0, 1, 2, ...) (1, 2, 3, ...)
ADDR1
DATA1
Device Transaction
(without byte lanes)
1 × 8-bit read
(EBI ignore the superfluous data)
1 × 16-bit read
2 × 16-bit read
1 × 8-bit write
(EBI read-modify-write)
1 × 16-bit write
2 × 16-bit write
RDHOLD IDLE
(0, 1, 2, ...)
16-bit External
1 × 16-bit read
1 × 16-bit read
2 × 16-bit read
1 × 16-bit read;
1 × 16-bit write
1 × 16-bit write
2 × 16-bit write
November 28, 2018