32-Bit Arm
®
Cortex
®
-M3 MCU
HT32F12345
I
2
S TX Data Register – I2STXDR
This register is used to specify the I
Offset :
0x00C
Reset value:
0x0000_0000
31
Type/Reset
WO
0 WO
23
Type/Reset
WO
0 WO
15
Type/Reset
WO
0 WO
7
Type/Reset
WO
0 WO
Bits
Field
[31:0]
TXDR
I
2
S RX Data Register – I2SRXDR
This register is used to store the I
Offset :
0x010
Reset value:
0x0000_0000
31
Type/Reset
RO
0 RO
23
Type/Reset
RO
0 RO
15
Type/Reset
RO
0 RO
7
Type/Reset
RO
0 RO
Bits
Field
[31:0]
RXDR
Rev. 1.10
2
S transmitted data.
30
29
28
0 WO
0 WO
22
21
20
0 WO
0 WO
14
13
12
0 WO
0 WO
6
5
4
0 WO
0 WO
Descriptions
TX Data Register
2
S received data.
30
29
28
0 RO
0 RO
22
21
20
0 RO
0 RO
14
13
12
0 RO
0 RO
6
5
4
0 RO
0 RO
Descriptions
RX Data Register
554 of 590
27
26
TXDR
0 WO
0 WO
0 WO
19
18
TXDR
0 WO
0 WO
0 WO
11
10
TXDR
0 WO
0 WO
0 WO
3
2
TXDR
0 WO
0 WO
0 WO
27
26
RXDR
0 RO
0 RO
0 RO
19
18
RXDR
0 RO
0 RO
0 RO
11
10
RXDR
0 RO
0 RO
0 RO
3
2
RXDR
0 RO
0 RO
0 RO
25
24
0 WO
0
17
16
0 WO
0
9
8
0 WO
0
1
0
0 WO
0
25
24
0 RO
0
17
16
0 RO
0
9
8
0 RO
0
1
0
0 RO
0
November 28, 2018
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