Holtek HT32F12345 User Manual page 14

32-Bit Arm ® Cortex ® -M3 MCU
HT32F12345
Register Map ..................................................................................................................... 471
Register Descriptions ......................................................................................................... 473
USB Control and Status Register - USBCSR .............................................................................. 473
USB Interrupt Enable Register - USBIER .................................................................................... 475
USB Interrupt Status Register - USBISR ..................................................................................... 476
USB Frame Count Register - USBFCR ....................................................................................... 477
USB Device Address Register - USBDEVAR .............................................................................. 478
USB Endpoint 0 Control and Status Register - USBEP0CSR ..................................................... 479
USB Endpoint 0 Interrupt Enable Register - USBEP0IER ........................................................... 480
USB Endpoint 0 Interrupt Status Register - USBEP0ISR ............................................................ 481
USB Endpoint 0 Transfer Count Register - USBEP0TCR ........................................................... 483
USB Endpoint 0 Configuration Register - USBEP0CFGR ........................................................... 484
USB Endpoint 1 ~ 3 Control and Status Register - USBEPnCSR, n = 1 ~ 3 ............................... 485
USB Endpoint 1 ~ 3 Interrupt Enable Register - USBEPnIER, n = 1 ~ 3 ..................................... 486
USB Endpoint 1 ~ 3 Interrupt Status Register - USBEPnISR, n = 1 ~ 3 ...................................... 487
USB Endpoint 1 ~ 3 Transfer Count Register - USBEPnTCR, n = 1 ~ 3 ..................................... 488
USB Endpoint 1 ~ 3 Configuration Register - USBEPnCFGR, n = 1 ~ 3 ..................................... 489
USB Endpoint 4 ~ 7 Control and Status Register - USBEPnCSR, n = 4 ~ 7 ............................... 490
USB Endpoint 4 ~ 7 Interrupt Enable Register - USBEPnIER, n = 4 ~ 7 ..................................... 492
USB Endpoint 4 ~ 7 Interrupt Status Register - USBEPnISR, n = 4 ~ 7 ...................................... 493
USB Endpoint 4 ~ 7 Transfer Count Register - USBEPnTCR, n = 4 ~ 7 ..................................... 494
USB Endpoint 4 ~ 7 Configuration Register - USBEPnCFGR, n = 4 ~ 7 ..................................... 495
24 Peripheral Direct Memory Access (PDMA) ..................................................... 496
Introduction ........................................................................................................................ 496
Features ............................................................................................................................. 496
Functional Description ....................................................................................................... 497
AHB Master .................................................................................................................................. 497
PDMA Channel ............................................................................................................................. 497
PDMA Request Mapping .............................................................................................................. 497
Channel transfer ........................................................................................................................... 498
Channel Priority ............................................................................................................................ 498
Transfer Request .......................................................................................................................... 499
Address Mode ............................................................................................................................... 499
Auto-Reload .................................................................................................................................. 500
Transfer Interrupt .......................................................................................................................... 500
Register Map ..................................................................................................................... 500
Register Descriptions ......................................................................................................... 503
PDMA Channel n Control Register - PDMACHnCR, n = 0 ~ 11 .................................................. 503
PDMA Channel n Source Address Register - PDMACHnSADR, n = 0 ~ 11 ................................ 505
PDMA Channel n Destination Address Register - PDMACHnDADR, n = 0 ~ 11 ......................... 505
PDMA Channel n Transfer Size Register - PDMACHnTSR, n = 0 ~ 11 ...................................... 506
PDMA Channel n Current Transfer Size Register - PDMACHnCTSR, n = 0 ~ 11 ....................... 507
PDMA Interrupt Status Register 0 - PDMAISR0 .......................................................................... 508
Rev. 1.10 14 of 590 November 28, 2018