Timer Pdma/Interrupt Control Register - Dictr - Holtek HT32F12345 User Manual

32-Bit Arm ® Cortex ® -M3 MCU
HT32F12345
Timer PDMA/Interrupt Control Register – DICTR
This register contains the timer PDMA and interrupt enable control bits.
Offset: 0x074
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
Type/Reset
7
Type/Reset
Bits Field
[26] TEVDE
[24] UEVDE
[19] CH3CCDE
[18] CH2CCDE
[17] CH1CCDE
[16] CH0CCDE
[10] TEVIE
[8] UEVIE
[3] CH3CCIE
Rev. 1.10
30 29 28
Reserved
22 21 20
Reserved
14 13 12
Reserved
6 5 4
Reserved
Descriptions
Trigger event PDMA Request Enable
0: Trigger PDMA request is disabled
1: Trigger PDMA request is enabled
Update event PDMA Request Enable
0: Update event PDMA request is disabled
1: Update event PDMA request is enabled
Channel 3 Capture / Compare PDMA Request Enable
0: Channel 3 PDMA request is disabled
1: Channel 3 PDMA request is enabled
Channel 2 Capture / Compare PDMA Request Enable
0: Channel 2 PDMA request is disabled
1: Channel 2 PDMA request is enabled
Channel 1 Capture / Compare PDMA Request Enable
0: Channel 1 PDMA request is disabled
1: Channel 1 PDMA request is enabled
Channel 0 Capture / Compare PDMA Request Enable
0: Channel 0 PDMA request is disabled
1: Channel 0 PDMA request is enabled
Trigger event Interrupt Enable
0: Trigger interrupt is disabled
1: Trigger interrupt is enabled
Update event Interrupt Enable
0: Update event interrupt is disabled
1: Update event interrupt is enabled
Channel 3 Capture / Compare Interrupt Enable
0: Channel 3 interrupt is disabled
1: Channel 3 interrupt is enabled
272 of 590
27 26
TEVDE Reserved
RW 0
19 18
CH3CCDE CH2CCDE CH1CCDE CH0CCDE
RW 0 RW 0 RW
11 10
TEVIE Reserved
RW 0
3 2
CH3CCIE CH2CCIE CH1CCIE
RW 0 RW 0 RW
25 24
UEVDE
RW 0
17 16
0 RW 0
9 8
UEVIE
RW 0
1 0
CH0CCIE
0 RW 0
November 28, 2018