System Architecture; Arm ® Cortex ® -M3 Processor - Holtek HT32F12345 User Manual

32-Bit Arm ® Cortex ® -M3 MCU
HT32F12345
3

System Architecture

The system architecture of the device that includes the Arm
and memory organization will be described in the following sections. The Cortex
generation processor core which offers many new features. Integrated and advanced features make
the Cortex ® -M3 processor suitable for high performance and low power microcontroller market.
In brief, Cortex
All memory accesses of Cortex
purpose and target memory space. The memory organization with Harvard architecture, pre-
defined memory map and up to 4 GB memory space makes the system flexible and extendable.
Arm Cortex -M3 Processor
® ®
Cortex ® -M3 is a general purpose 32-bit processor core which very suitable for high performance
and low power microcontroller market. It offers many new features including a Thumb-2
instruction sets, hardware divide, low latency interrupt response time, atomic bit-banding access
and multiple buses for simultaneous accesses. Cortex
supports both Thumb and Thumb-2 instruction sets. Some system peripherals are also provided by
the Cortex ® -M3 including:
▄
Internal Bus Matrix connected with ICode bus, DCode bus, System bus, Private Peripheral Bus
(PPB) and debug accesses (AHB-AP)
▄
Nested Vectored Interrupt Controller (NVIC)
▄
Flash Patch and Breakpoint (FPB)
▄
Data Watchpoint and Trace (DWT)
▄
Instrument Trace Macrocell (ITM)
▄
Memory Protection Unit (MPU)
▄
Serial Wire JTAG Debug Port (SWJ-DP)
▄
Embedded Trace Macrocell (ETM)
▄
Trace Port Interface Unit (TPIU)
The following figure shows the Cortex
Arm ® Cortex ® -M3 Technical Reference Manual.
Rev. 1.10
® -M3 processor includes three AHB-Lite buses, ICode, DCode and System bus.
® -M3 are performed on those three buses according to the different
® -M3 block diagram. For more information, please refer to
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® Cortex ® -M3 processor, bus architecture
-M3 is based on ARMv7 architecture and
®
November 28, 2018
® -M3 is a next