32-Bit Arm
®
Cortex
®
-M3 MCU
HT32F12345
Register Descriptions
EXTI Interrupt Configuration Register n – EXTICFGRn, n = 0 ~ 15
This register is used to specify the de-bounce function and select the trigger type.
Offset:
0x000 (0) ~ 0x03C (15)
Reset value: 0x0000_0000
31
DBnEN
Type/Reset
RW
0 RW
23
Type/Reset
15
Type/Reset
RW
0 RW
7
Type/Reset
RW
0 RW
Bits
Field
[31]
DBnEN
[30:28]
SRCnTYPE
[15:0]
DBnCNT
Rev. 1.10
30
29
28
SRCnTYPE
0 RW
0 RW
22
21
20
14
13
12
0 RW
0 RW
6
5
4
0 RW
0 RW
Descriptions
EXTIn De-bounce Circuit Enable Bit (n = 0 ~ 15)
0: De-bounce circuit is disabled
1: De-bounce circuit is enabled
EXTIn Interrupt Source Trigger Type (n = 0 ~ 15)
SRCnTYPE [2:0]
0
0
0
Low-level Sensitive
0
0
1
High-level Sensitive
0
1
0
Negative-edge Triggered
0
1
1
Positive-edge Triggered
1
X
X
Both-edge Triggered
EXTIn De-bounce Counter (n = 0 ~ 15)
The de-bounce time is calculated with DBnCNT × APB clock (EXTI_PCLK) period
and should be long enough to take effect on the input signal.
175 of 590
27
26
Reserved
0
19
18
Reserved
11
10
DBnCNT
0 RW
0 RW
0 RW
3
2
DBnCNT
0 RW
0 RW
0 RW
Interrupt Source Type
25
24
17
16
9
8
0 RW
0
1
0
0 RW
0
November 28, 2018
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