Clock Control Register - Clkcr - Holtek HT32F12345 User Manual

32-Bit Arm ® Cortex ® -M3 MCU
HT32F12345
Clock Control Register – CLKCR
This register is used to configure the SD clock frequency and enable control.
Offset: 0x038
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
Type/Reset RW 0 RW
7
Type/Reset
Bits Field
[15:8] CLKPRE
[3] CLKDUTY
[2] CLKEN
[1] CLKSPEN
[0] CLKSPLV
Rev. 1.10
30 29 28
22 21 20
14 13 12
0 RW 0 RW
6 5 4
Reserved
Descriptions
SD Clock Prescaler
00h: SD_CLK = CK_AHB
01h: SD_CLK = CK_AHB / 2
02h: SD_CLK = CK_AHB / 3
...
FFh: SD_CLK = CK_AHB / 256
SD Clock Duty Cycle
0: Higher
1: Lower
If the SD_CLK prescaler is not a multiple of 2, set this bit to 1 to obtain a lower
duty cycle.
SD Clock Enable
0: Disable
1: Enable
The Host Controller should stop the SD_CLK when this bit is set to 0.
SD Clock Stop Enable
0: Disable
1: Enable
If this bit is set to 1, the SD_CLK will remain high or low level when the SD bus
is idle.
SD Clock Stop Level
0: Low Level
1: High Level
If the SD Clock Stop function is enabled, the SD_CLK will remain at a high level
when this bit is set to 1 and vice versa.
581 of 590
27 26
Reserved
19 18
Reserved
11 10
CLKPRE
0 RW 0 RW 0 RW
3 2
CLKDUTY CLKEN CLKSPEN CLKSPLV
RW 0 RW 0 RW
25 24
17 16
9 8
0 RW 0
1 0
0 RW 0
November 28, 2018