Holtek HT32F12345 User Manual page 404

32-Bit Arm ® Cortex ® -M3 MCU
HT32F12345
Bits Field
[10] BUSERR
[9] RXNACK
[8] ARBLOS
[3] GCS
[2] ADRS
[1] STO
Rev. 1.10
Descriptions
Bus Error Flag
0: No bus error has occurs
1: Bus error has occurred
This bit is set by hardware when the I
condition in a transfer process. Writing a "1" to this bit will clear the BUSERR flag.
In Master Mode: Once the Bus Error event occurs, both the SDA and SCL lines are
released by hardware and the BUSERR flag is asserted. The application software
has to clear the BUSERR flag before the next address byte is transmitted.
In Slave Mode: Once a misplaced START or STOP condition has been detected by
the slave device, the software must clear the BUSERR flag before the next address
byte is received.
Received Not Acknowledge Flag
0: Acknowledge is returned from receiver
1: Not Acknowledge is returned from receiver
The RXNACK bit indicates that the not Acknowledge signal is received in master or
slave transmitter mode. Writing "1" to this bit will clear the RXNACK flag.
Arbitration Loss Flag
0: No arbitration loss is detected
1: Bit arbitration loss is detected
This bit is set by hardware on the current clock which the I
arbitration to another master during the address or data frame transmission. Writing
"1" to this bit will clear the ARBLOS flag. Once the ARBLOS flag is asserted by
hardware, the ARBLOS flag must be cleared before the next transmission.
General Call Slave Flag
0: No general call slave occurs
1: I 2 C interface is addressed by a general call command
When the I 2 C interface receives an address with a value of 0x00 or 0x000 in the 7-bit
or 10-bit addressing mode, if both the GCEN and the AA bit are set to 1, then it is
switched as a general call slave. This flag is cleared automatically after being read.
Address Transmit (master mode) / Address Receive (slave mode) Flag
Address Sent in Master Mode
0: Address frame has not been transmitted
1: Address frame has been transmitted
For the 7-bit addressing mode, this bit is set after the master device receives the
address frame acknowledge bit sent from the slave device. For the 10-bit addressing
mode, this bit is set after receiving the acknowledge bit of the first header byte and
the second address.
Address Matched in Slave Mode
0: I 2 C interface is not addressed
1: I 2 C interface is addressed as slave
When the I 2 C interface has received the calling address that matches the address
defined in the I2CADDR register together with the AA bit being set to 1 in the I2CCR
register, it will be switched to a slave mode. This flag is cleared automatically after
the I2CSR register has been read.
STOP Condition Detected Flag
0: No STOP condition detected
1: STOP condition detected in slave mode
This bit is only available for the slave mode and is cleared automatically after the
I2CSR register is read.
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2 C interface detects a misplaced START or STOP
2 C interface loses the bus
November 28, 2018