32-Bit Arm
®
Cortex
®
-M3 MCU
HT32F12345
●
Supports byte, half-word and word data size
●
Programmable CRC initial seed value
●
CRC computation done in 1 AHB clock cycle for 8-bit data and 4 AHB clock cycles for 32-bit
data
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Supports PDMA to complete a CRC computation of a block of memory
▄
Peripheral Direct Memory Access – PDMA
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12 channels with trigger source grouping
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8/16/32-bit width data transfer
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Supports Address increment, decrement or fixed mode
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4-level programmable channel priority
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Auto reload mode
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Supported trigger source: ADC, SPI, EBI, CRC, USART, UART, I
SDIO and software request
▄
External Bus Interface – EBI
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Programmable interface for various memory types
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Translates the AHB transactions into the appropriate external device protocol
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4 Memory bank regions and independent chip select control for each memory bank
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Accurate control of setup, strobe, hold and turn-around timing per memory bank
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Supports page mode read
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Automatic translation when AHB transaction width and external memory interface width is
different
●
Write buffer to decrease the stalling of the AHB write burst transaction
●
Both multiplexed and non-multiplexed address and data line configurations
– Up to 21 address lines
– Up to 16-bit data bus width
▄
Universal Serial Bus Device Controller – USB
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Complies with USB 2.0 full-speed (12 Mbps) specification
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On-chip USB full-speed transceiver
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1 control endpoint (EP0) for control transfer
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3 single-buffered endpoint (EP1 ~ EP3) for bulk and interrupt transfer
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4 double-buffered endpoint (EP4 ~ EP7) for bulk, interrupt and isochronous transfer
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1 KB EP_SRAM used as the endpoint data buffers
▄
Secure Digital Input Output Interface – SDIO
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Supports two different data bus modes: 1-bit (default) and 4-bit
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Supports two different speed modes: Normal speed (default) and High speed
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SD clock frequency of up to 48 MHz
●
SPI mode and MMC stream mode not supported
▄
Debug support
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Serial Wire Debug Port SW-DP
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6 instruction comparator and 2 literal comparator for hardware breakpoint/watchpoint or code
patch
●
1-bit asynchronous trace (TRACESWO)
▄
Package and Operation Temperature
●
46-pin QFN, 48/64-pin LQFP package
●
Operation temperature range: -40 ºC to 85 ºC
Rev. 1.10
31 of 590
C, I
S, GPTM, MCTM,
2
2
November 28, 2018
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