Backup Domain Control Register - Bakcr - Holtek HT32F12345 User Manual

32-Bit Arm ® Cortex ® -M3 MCU
HT32F12345
Backup Domain Control Register – BAKCR
This register provides power control bits for the Deep-Sleep and Power-Down modes.
Offset: 0x104
Reset value: 0x0000_0000 (Reset only by Backup Domain reset)
31
Type/Reset
23
Type/Reset
15
DMOSSTS
Type/Reset RO 0
7
DMOSON Reserved
Type/Reset RW 0
Bits Field
[15] DMOSSTS
[12] V15RDYSC V
[9] WUPIEN
Rev. 1.10
30 29 28
22 21 20
14 13 12
Reserved V15RDYSC
RW
6 5 4
LDOFTRM
RW 0 RW
Descriptions
Depletion MOS Status
This bit is set to 1 if the DMOSON bit in this register has been set to 1.
This bit is cleared to 0 if the DMOSON bit has been set to 0 or if a POR / PDR reset
occurred.
Ready Source Selection.
DD15
0: BKISO bit in the LPCR register located in the CKCU
1: V POR
DD15
Setting this bit to determine what control signal of isolation cells is used to disable
the isolation function of the V
External WAKEUP Pin Interrupt Enable
0: Disable WAKEUP pin interrupt function
1: Enable WAKEUP pin interrupt function
The software can set the WUPIEN bit to 1 to assert the LPWUP interrupt in the NVIC
unit when both the WUPEN and WUPF bits are set to1.
77 of 590
27 26
Reserved
19 18
Reserved
11 10
Reserved
0
3 2
LDOOFF LDOLCM
0 RW 0 RW
to V power domain level shifter.
DD15 DD
25 24
17 16
9 8
WUPIEN WUPEN
RW 0 RW 0
1 0
Reserved BAKRST
0 WO 0
November 28, 2018