Apb Peripheral Reset Register 0; Apbprstr0 - Holtek HT32F12345 User Manual

32-Bit Arm ® Cortex ® -M3 MCU
HT32F12345
Bits Field
[5] USBRST
[0] DMARST

APB Peripheral Reset Register 0

This register specifies several APB peripherals software reset control bits.
Offset: 0x108
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
EXTIRST
Type/Reset RW 0 RW
7
Type/Reset
Bits Field
[25] I2SRST
[15] EXTIRST
[14] AFIORST
[11] UR1RST
[10] UR0RST
Rev. 1.10
Descriptions
USB Reset Control
0: No reset
1: Reset USB
This bit is set by software and cleared to 0 by hardware automatically.
Peripheral DMA (PDMA) Reset Control
0: No reset
1: Reset Peripheral DMA (PDMA)
This bit is set by software and cleared to 0 by hardware automatically.
–
30 29
Reserved
22 21
14 13
AFIORST Reserved
0
6 5
Reserved SPI1RST SPI0RST
RW 0 RW
Descriptions
I 2 S Reset Control
0: No reset
1: Reset I 2 S
This bit is set by software and cleared to 0 by hardware automatically.
External Interrupt Controller Reset Control
0: No reset
1: Reset EXTI
This bit is set by software and cleared to 0 by hardware automatically.
Alternate Function I/O Reset Control
0: No reset
1: Reset Alternate Function I/O
This bit is set by software and cleared to 0 by hardware automatically.
UART1 Reset Control
0: No reset
1: Reset UART1
This bit is set by software and cleared to 0 by hardware automatically.
UART0 Reset Control
0: No reset
1: Reset UART0
This bit is set by software and cleared to 0 by hardware automatically.
121 of 590

APBPRSTR0

28 27 26
20 19 18
Reserved
12 11 10
UR1RST UR0RST
RW 0 RW
4 3 2
Reserved
0
25 24
I2SRST Reserved
RW 0
17 16
9 8
USR1RST USR0RST
0 RW 0 RW 0
1 0
I2C1RST I2C0RST
RW 0 RW 0
November 28, 2018