I 2 S Interrupt Enable Register - I2Sier - Holtek HT32F12345 User Manual

32-Bit Arm ® Cortex ® -M3 MCU
HT32F12345
I 2 S Interrupt Enable Register – I2SIER
This register contains the corresponding I
Offset : 0x004
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
Type/Reset
7
Reserved
Type/Reset RW
Bits Field
[6] RXOVIEN
[5] RXUDIEN
[4] RXFTLIEN
[2] TXOVIEN
[1] TXUDIEN
[0] TXFTLIEN
Rev. 1.10
2 S interrupt enable bits.
30 29
22 21
14 13
6 5
RXOVIEN RXUDIEN RXFTLIEN Reserved
0 RW 0 RW
Descriptions
RX FIFO Overflow Interrupt Enable
0: Disable
1: Enable
RX FIFO Underflow Interrupt Enable
0: Disable
1: Enable
RX FIFO Trigger Level Interrupt Enable
0: Disable
1: Enable
TX FIFO Overflow Interrupt Enable
0: Disable
1: Enable
TX FIFO Underflow Interrupt Enable
0: Disable
1: Enable
TX FIFO Trigger Level Interrupt Enable
0: Disable
1: Enable
552 of 590
28 27 26
Reserved
20 19 18
Reserved
12 11 10
Reserved
4 3 2
TXOVIEN
0 RW
25 24
17 16
9 8
1 0
TXUDIEN TXFTLIEN
0 RW 0 RW 0
November 28, 2018