Figure 108. Update Event 1 Setup Diagram; Figure 109. Chxe, Chxne And Chxom Updated By Update Event 2 - Holtek HT32F12345 User Manual

32-Bit Arm ® Cortex ® -M3 MCU
HT32F12345
Update Event 1
The UEV1DIS bit in the CNTCFR register can determine whether an update event 1 occurs or
not. When the update event 1 occurs, the corresponding update event interrupt will be generated
depending upon whether the update event 1 interrupt generation function is enabled or not by
configuring the UGDIS bit in the CNTCFR register. For a more detailed description, refer to the
UEV1DIS and UGDIS bit definition in the CNTCFR register.
Update Event 1 Management
Counter Overflow / Underflow
UEV1G
Slave Restart mode
Update Event 1 Interrupt Management
Counter Overflow / Underflow
UEV1G
Slave Restart mode

Figure 108. Update Event 1 Setup Diagram

Update Event 2
The CHxE, CHxNE, CHxOM control bits for the complementary outputs can be preloaded by
setting the COMPRE bit in the CTR register. Here the shadow bits of the CHxE, CHxNE, CHxOM
bits will be updated when an update event 2 occurs.
COMPRE = 1, CHOSSR = 1, CHxP = CHxNP = 0, CHDTG = 0
Update Event 2
CHxE
CHxNE
Shadow CHxE
Shadow CHxNE
PWM1
CHxOM
Shadow CHxOM
CHxO
CHxNO

Figure 109. CHxE, CHxNE and CHxOM Updated by Update Event 2

Rev. 1.10
UGDIS
Forced Inactive
Forced Inactive
PWM1
314 of 590
UEV1 (Update PSCR,
CRR, CHxCCR, CHxACR
Shadow Registers)
UEV1DIS
UEV1 interrupt
UEV1DIS
Forced Active
Forced Active
November 28, 2018