Holtek HT32F12345 User Manual page 351

32-Bit Arm ® Cortex ® -M3 MCU
HT32F12345
Bits Field
[11:8] BKF0
[6] BK1SEL
[5] CHAOE
[4] CHMOE
[3] BKP1
[2] BKE1
[1] BKP0
[0] BKE0
Rev. 1.10
Descriptions
Break 0 Input Filter Setting
These bits define the frequency ratio used to sample the MTn_BRK0 signal. The
digital filter in the MCTM is an N-event counter where N is defined as how many
valid transitions are necessary to output a filtered signal.
0000: No filter – don't need sample clock
0001: f = f , N = 2
SAMPLING CLKIN
0010: f = f , N = 4
SAMPLING CLKIN
0011: f = f , N = 8
SAMPLING CLKIN
0100: f = f / 2, N = 6
SAMPLING DTS
0101: f = f / 2, N = 8
SAMPLING DTS
0110: f = f / 4, N = 6
SAMPLING DTS
0111: f = f / 4, N = 8
SAMPLING DTS
1000: f = f / 8, N = 6
SAMPLING DTS
1001: f = f / 8, N = 8
SAMPLING DTS
1010: f = f / 16, N = 5
SAMPLING DTS
1011: f = f / 16, N = 6
SAMPLING DTS
1100: f = f / 16, N = 8
SAMPLING DTS
1101: f = f / 32, N = 5
SAMPLING DTS
1110: f = f / 32, N = 6
SAMPLING DTS
1111: f = f / 32, N = 8
SAMPLING DTS
Break 1 Selection
0: ETI signal is selected for the MTn_ETI pin
1: MTn_BRK1 signal is selected for the MTn_ETI pin
Note: The Break 1 and ETI signal are share with the same MTn_ETI pin. This control
bit can switch the pin function for the second break signal of the MCTM.
Channel Automatic Output Enable
0: CHMOE can be set only by software
1: CHMOE can be set by software or automatically by an update event
Channel Main Output Enable
Cleared asynchronously by hardware on a break event occurrence.
0: MTn_CHxO and MTn_CHxNO are disabled or forced to an idle state
1: MTn_CHxO and MTn_CHxNO are enabled if the enable bits (CHxE, CHxNE)
are set
Break 1 Input Polarity
0: Break input is active low
1: Break input is active high
Break 1 Enable
0: Break inputs is disabled
1: Break inputs is enabled
Break 0 Input Polarity
0: Break input is active low
1: Break input is active high
Break 0 Enable
0: Break inputs is disabled
1: Break inputs is enabled
351 of 590 November 28, 2018