Digital Filter; Figure 63. Both Ti0 And Ti1 Quadrature Decoder Counting; Figure 64. Gtn_Eti Pin Digital Filter Diagram With N = 2 - Holtek HT32F12345 User Manual

32-Bit Arm ® Cortex ® -M3 MCU
HT32F12345
TI0
TI1
Up
Down

Figure 63. Both TI0 and TI1 Quadrature Decoder Counting

Digital Filter

The digital filters are embedded in the input stage and clock controller block for the GTn_CH0 ~
GTn_CH3 and GTn_ETI pins respectively. The digital filter in the GPTM is an N-event counter
where N refers to how many valid transitions are necessary to output a filtered signal. The N value
can be 0, 2, 4, 5, 6 or 8 according to the user selection for each filter.
Digital Filter (N=2)
ETIP
D
CK
fsampling

Figure 64. GTn_ETI Pin Digital Filter Diagram with N = 2

Rev. 1.10
Q D Q D Q
CK CK
242 of 590
Quadrature Decoder
Counting on Both TI0 & TI1
(CH0P = 0, CH1P = 0)
No Filtered
J Q
CK
K
Filtered
November 28, 2018