Adc High Priority Conversion List Register - Adchlst - Holtek HT32F12345 User Manual

32-Bit Arm ® Cortex ® -M3 MCU
HT32F12345
ADC High Priority Conversion List Register – ADCHLST
This register specifies the conversion sequence order No.0 ~ No.3 of the ADC high priority group.
Offset: 0x020
Reset value: 0x0000_0000
31
Reserved
Type/Reset
23
Reserved
Type/Reset
15
Reserved
Type/Reset
7
Reserved
Type/Reset
Bits Field
[28:24] ADHSEQ3
[20:16] ADHSEQ2
[12:8] ADHSEQ1
[4:0] ADHSEQ0
Rev. 1.10
30 29 28
RW
22 21 20
RW
14 13 12
RW
6 5 4
RW
Descriptions
ADC High Priority Conversion Sequence Select 3
Select ADC input channel of 3rd sequence in ADC high priority conversion mode.
0x0: ADC_IN0
0x1: ADC_IN1
0x2: ADC_IN2
0x3: ADC_IN3
0x4: ADC_IN4
0x5: ADC_IN5
0x6: ADC_IN6
0x7: ADC_IN7
0x8: ADC_IN8
0x9: ADC_IN9
0xA: ADC_IN10
0xB: ADC_IN11
0x10: Analog ground, VSSA (V
0x11: Analog power, VDDA (V
0xC ~ 0xF / 0x12 ~ 0x1F: Invalid setting. These values must not be selected as it
may cause the ADC abnormal operations.
ADC High Priority Conversion Sequence Select 2
ADC High Priority Conversion Sequence Select 1
ADC High Priority Conversion Sequence Select 0
199 of 590
27 26
ADHSEQ3
0 RW 0 RW 0 RW
19 18
ADHSEQ2
0 RW 0 RW 0 RW
11 10
ADHSEQ1
0 RW 0 RW 0 RW
3 2
ADHSEQ0
0 RW 0 RW 0 RW
)
REF-
)
REF+
25 24
0 RW 0
17 16
0 RW 0
9 8
0 RW 0
1 0
0 RW 0
November 28, 2018