Channel 2 Output Configuration Register - Ch2Ocfr - Holtek HT32F12345 User Manual

32-Bit Arm ® Cortex ® -M3 MCU
HT32F12345
Bits Field
[8][2:0] CH1OM[3:0] Channel 1 Output Mode Setting
Channel 2 Output Configuration Register – CH2OCFR
This register specifies the channel 2 output mode configuration.
Offset: 0x048
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
Type/Reset
7
Reserved
Type/Reset
Rev. 1.10
Descriptions
These bits define the functional types of the output reference signal CH1OREF.
0000: No Change
0001: Output 0 on compare match
0010: Output 1 on compare match
0011: Output toggles on compare match
0100: Force inactive – CH1OREF is forced to 0
0101: Force active – CH1OREF is forced to 1
0110: PWM mode 1
- During up-counting, channel 1 has an active level when CNTR <
CH1CCR or otherwise has an inactive level.
- During down-counting, channel 1 has an inactive level when CNTR >
CH1CCR or otherwise has an active level.
0111: PWM mode 2
- During up-counting, channel 1 has an inactive level when CNTR <
CH1CCR or otherwise has an active level.
- During down-counting, channel 1 has an active level when CNTR >
CH1CCR or otherwise has an inactive level.
1110: Asymmetric PWM mode 1
- During up-counting, channel 1 has an active level when CNTR <
CH1CCR or otherwise has an inactive level.
- During down-counting, channel 1 has an inactive level when CNTR >
CH1ACR or otherwise has an active level.
1111: Asymmetric PWM mode 2
- During up-counting, channel 1 has an inactive level when CNTR <
CH1CCR or otherwise has an active level.
- During down-counting, channel 1 has an active level when CNTR >
CH1ACR or otherwise has an inactive level
Note: When channel 1 is uesd as asymmetric PWM output mode, the Counter Mode
Selection bit in Counter Configuration Register must be configured as Center-
aligned Counting mode (CMSEL = 01 / 02 / 03).
30 29 28
22 21 20
14 13 12
Reserved
6 5 4
CH2IMAE CH2PRE
RW 0 RW
342 of 590
27 26
Reserved
19 18
Reserved
11 10
3 2
REF2CE
0 RW 0 RW 0 RW
25 24
17 16
9 8
CH2OM[3]
RW 0
1 0
CH2OM[2:0]
0 RW 0
November 28, 2018