Holtek HT32F12345 User Manual page 18

32-Bit Arm ® Cortex ® -M3 MCU
HT32F12345
List of Tables
Table 1. Features and Peripheral List .................................................................................................... 32
Table 2. Document Conventions ............................................................................................................. 34
Table 3. Register Map ............................................................................................................................. 39
Table 4. Flash Memory and Option Byte ................................................................................................. 44
Table 5. Relationship between Wait State Cycle and HCLK ................................................................... 44
Table 6. Booting Modes .......................................................................................................................... 45
Table 7. Option Byte Memory Map ......................................................................................................... 49
Table 8. Access Permission of Protected Main Flash Page .................................................................... 50
Table 9. Access Permission When Security Protection is Enabled ......................................................... 51
Table 10. FMC Register Map ................................................................................................................. 52
Table 11. Operation Mode Definitions ..................................................................................................... 73
Table 12. Enter / Exit Power Saving Modes ............................................................................................ 74
Table 13. Power Status after System Reset ........................................................................................... 75
Table 14. PWRCU Register Map ............................................................................................................ 75
Table 15. Output Divider 2 Value Mapping.............................................................................................. 87
Table 16. Feedback Divider 2 Value Mapping......................................................................................... 88
Table 17. USB PLL Output Divider 2 Value Mapping .............................................................................. 89
Table 18. USB PLL Feedback Divider 2 Value Mapping ......................................................................... 89
Table 19. CKOUT Clock Source ............................................................................................................. 92
Table 20. CKCU Register Map ................................................................................................................ 92
Table 21. RSTCU Register Map ............................................................................................................118
Table 22. AFIO, GPIO and I/O Pad Control Signal True Table.............................................................. 126
Table 23. GPIO Register Map ............................................................................................................... 127
Table 24. AFIO Selection for Peripheral Map Example ......................................................................... 161
Table 25. AFIO Register Map ................................................................................................................ 161
Table 26. Exception types ..................................................................................................................... 166
Table 27. NVIC Register Map ............................................................................................................... 169
Table 28. EXTI Register Map ................................................................................................................ 174
Table 29. Data Format in ADCDRy [15:0] (y = 0 ~ 11) and ADCHDRy [15:0] (y = 0 ~ 3)...................... 190
Table 30. A/D Converter Register Map ................................................................................................. 191
Table 31. CMP Register Map ................................................................................................................ 218
Table 32. Counting Direction and Encoding Signals ............................................................................. 241
Table 33. Register Map of GPTM ......................................................................................................... 250
Table 34. GPTM Internal Trigger Connection ....................................................................................... 256
Table 35. BFTM Register Map .............................................................................................................. 287
Table 36. Compare Match Output Setup .............................................................................................. 305
Table 37. Output Control Bits for Complementary Output with a Break Event Occurrence .................. 313
Table 38. Counting Direction and Encoding Signals ............................................................................. 316
Table 39. Lock Level Table.................................................................................................................... 324
Rev. 1.10 18 of 590 November 28, 2018