Register Descriptions; Timer Counter Configuration Register - Cntcfr - Holtek HT32F12345 User Manual

32-Bit Arm ® Cortex ® -M3 MCU
HT32F12345

Register Descriptions

Timer Counter Configuration Register – CNTCFR
This register specifies the GPTM counter configuration.
Offset: 0x000
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
Type/Reset
7
Type/Reset
Bits Field
[24] DIR
[17:16] CMSEL
[9:8] CKDIV
[1] UGDIS
Rev. 1.10
30 29 28
Reserved
22 21 20
Reserved
14 13 12
Reserved
6 5 4
Reserved
Descriptions
Counting Direction
0: Count-up
1: Count-down
Note: This bit is read only when the Timer is configured to be in the Center-aligned
mode or when used as a Quadrature decoder
Counter Mode Selection
00: Edge aligned mode. Normal up-counting and down-counting available for
this mode. Counting direction is defined by the DIR bit.
01: Center aligned mode 1. The counter counts up and down alternatively. The
compare match interrupt flag is set during the count-down period.
10: Center aligned mode 2. The counter counts up and down alternatively. The
compare match interrupt flag is set during the count-up period.
11: Center aligned mode 3. The counter counts up and down alternatively. The
compare match interrupt flag is set during the count-up and count-down
period.
Clock Division
These two bits define the frequency ratio between the timer clock (f
time clock (f ). The dead-time clock is also used for digital filter sampling clock.
DTS
00: f = f
DTS CLKIN
01: f = f / 2
DTS CLKIN
10: f = f / 4
DTS CLKIN
11: Reserved
Update event interrupt generation disable control
0: Any of the following events will generate an update PDMA request or interrupt
- Counter overflow / underflow
- Setting the UEVG bit
- Update generation through the slave mode
1: Only counter overflow / underflow generates an update PDMA request or
interrupt
251 of 590
27 26 25
19 18 17
RW
11 10 9
RW
3 2 1
UGDIS
RW
CLKIN
November 28, 2018
24
DIR
RW 0
16
CMSEL
0 RW 0
8
CKDIV
0 RW 0
0
UEVDIS
0 RW 0
) and dead-