Usb Frame Count Register - Usbfcr - Holtek HT32F12345 User Manual

32-Bit Arm ® Cortex ® -M3 MCU
HT32F12345
Bits Field
[2] URSTIF
[1] SOFIF
USB Frame Count Register – USBFCR
This register specifies the lost Start-of-Frame number and the USB frame count.
Offset: 0x00C
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
Type/Reset
7
Type/Reset RO 0 RO
Bits Field
[18:17] LSOF
Rev. 1.10
Descriptions
USB Reset Interrupt Flag
This bit is set by the hardware when the USB reset has been detected. When a
USB reset occurs, the internal protocol state machine will be reset and an USB
reset interrupt will be generated if the URSTIE bit in the USBIER register is set to
1. Data reception and transmission are disabled until the URSTIF bit is cleared
to 0. The USB configuration related registers ( USBCSR, USBIER, USBISR,
USBFCR and USBDEVAR) will not be reset by a USB reset event except for the
USB device address (USBDEVAR), this is to ensure that a USB reset interrupt can
be safely excited and any data transactions immediately followed by the USB reset
can be completely accessed by the software. Therefore the microcontroller must
properly reset these registers. The USB endpoint related registers (USBEPnCSR,
USBEPnISR and USBEPnTCR) are also reset by a USB reset event, however, the
endpoint configuration (USBEPnCFGR) and interrupt enable (USBEPnIER) registers
are not affected by the USB reset event and will remain unchanged.
This bit is cleared to 0 by writing 1.
SOF Interrupt Flag
This bit is set by the hardware when a start-of-frame packet has been received.
This bit is cleared to 0 by writing 1.
30 29 28
22 21 20
Reserved
14 13 12
Reserved
6 5 4
0 RO 0 RO
Descriptions
Lost Start-of-Frame number
These bits are written and incremented by 1 by the hardware each time the ESOFIF
bit is set. It is used to count the number of lost SOF packets. When a SOF packet
has been received, these bits are cleared.
477 of 590
27 26
Reserved
19 18
RO 0 RO
11 10
RO 0 RO
3 2
FRNUM
0 RO 0 RO 0 RO
25 24
17 16
LSOF SOFLCK
0 RO 0
9 8
FRNUM
0 RO 0
1 0
0 RO 0
November 28, 2018