Holtek HT32F12345 User Manual page 401

32-Bit Arm ® Cortex ® -M3 MCU
HT32F12345
Bits Field
[8] ARBLOSIE
[3] GCSIE
[2] ADRSIE
[1] STOIE
[0] STAIE
Rev. 1.10
Descriptions
Arbitration Loss Interrupt Enable Bit in the I2C multi-master mode
0: Interrupt disabled
1: Interrupt enabled
When the I2CEN bit in the I2CCR register is cleared to 0, this bit is cleared to 0 by
hardware.
General Call Slave Interrupt Enable Bit
0: Interrupt disabled
1: Interrupt enabled
When the I2CEN bit in the I2CCR register is cleared to 0, this bit is cleared to 0 by
hardware.
Slave Address Match Interrupt Enable Bit
0: Interrupt disabled
1: Interrupt enabled
When the I2CEN bit in the I2CCR register is cleared to 0, this bit is cleared to 0 by
hardware.
STOP Condition Detected Interrupt Enable Bit
0: Interrupt disabled
1: Interrupt enabled
When the I2CEN bit in the I2CCR register is cleared to 0, this bit is cleared to 0 by
hardware. The bit is used for the I2C slave mode only.
START Condition Transmit Interrupt Enable Bit
0: Interrupt disabled
1: Interrupt enabled
When the I2CEN bit in the I2CCR register is cleared to 0, this bit is cleared to 0 by
hardware. The bit is used for the I2C master mode only.
401 of 590 November 28, 2018