Register Descriptions; Ebi Control Register - Ebicr - Holtek HT32F12345 User Manual

32-Bit Arm ® Cortex ® -M3 MCU
HT32F12345

Register Descriptions

EBI Control Register – EBICR
This register specifies the control setting for EBI bank.
Offset: 0x000
Reset value: 0x0000_0000
31
Type/Reset RW 0 RW
23
ARDYTDIS3 ARDYEN3 ARDYTDIS2 ARDYEN2 ARDYTDIS1 ARDYEN1 ARDYTDIS0 ARDYEN0
Type/Reset RW 0 RW
15
NOIDLE3 NOIDLE2
Type/Reset RW 0 RW
7
Type/Reset RW 0 RW
Bits Field
[31:28] IDLET
[27] BLEN3
[26] BLEN2
[25] BLEN1
[24] BLEN0
[23] ARDYTDIS3 Asynchronous Ready Timeout Disable 3
Rev. 1.10
30 29 28
IDLET
0 RW 0 RW
22 21 20
0 RW 0 RW
14 13 12
NOIDLE1 NOIDLE0 BANKEN3 BANKEN2 BANKEN1 BANKEN0
0 RW 0 RW
6 5 4
Mode3 Mode2
0 RW 0 RW
Descriptions
IDLE Time
Sets the number of cycles between EBI transactions. If set to 0, one cycle is inserted
by the hardware. The cycle unit is based on the HCLK clock period.
Byte Lane Enable 3
0: Disable EBI byte lane functionality
1: Enable EBI byte lane functionality
Enable or disable byte lane functionality for bank 3.
Byte Lane Enable 2
0: Disable EBI byte lane functionality
1: Enable EBI byte lane functionality
Enable or disable byte lane functionality for bank 2.
Byte Lane Enable 1
0: Disable EBI byte lane functionality
1: Enable EBI byte lane functionality
Enable or disable byte lane functionality for bank 1.
Byte Lane Enable 0
0: Disable EBI byte lane functionality
1: Enable EBI byte lane functionality
Enable or disable byte lane functionality for bank 0.
0: Enable EBI asynchronous ready timeout control functionality
1: Disable EBI asynchronous ready timeout control functionality
Enable or disable the asynchronous ready timeout functionality for bank 3. The
default asynchronous ready timeout period is 32 HCLK clock cycles and cannot be
changed.
528 of 590
27 26
BLEN3 BLEN2
0 RW 0 RW 0 RW
19 18
0 RW 0 RW 0 RW
11 10
0 RW 0 RW 0 RW
3 2
Mode1
0 RW 0 RW 0 RW
25 24
BLEN1 BLEN0
0 RW 0
17 16
0 RW 0
9 8
0 RW 0
1 0
Mode0
0 RW 0
November 28, 2018