Figure 69. Pausing Gptm1 Using The Gptm0 Ch0Oref Signal; Figure 70. Triggering Gptm1 With Gptm0 Update Event - Holtek HT32F12345 User Manual

32-Bit Arm ® Cortex ® -M3 MCU
HT32F12345
Master GPTM0
f
CLKIN
GPTM0
CH0OREF
GPTM0
32
CNTR
Slave GPTM1
GPTM1
CNTR
GPTM1
TEVIF

Figure 69. Pausing GPTM1 Using the GPTM0 CH0OREF Signal

Using one timer to trigger another timer start counting
▄
Configure GPTM0 to operate in the master mode to send its Update Event UEV as the trigger
output (MMSEL = 0x02).
▄
Configure the GPTM0 period by setting the CRR register.
▄
Configure GPTM1 to get the input trigger source from the GPTM0 trigger output (TRSEL = 0x09).
▄
Configure GPTM1 to be in the slave trigger mode (SMSEL = 0x06).
▄
Start GPTM0 by writing '1' to the TME bit.
f
CLKIN
GPTM0
UEVIF
GPTM0
13
CNTR
GPTM1
CNTR
GPTM1
TME bit
GPTM1
TEVIF

Figure 70. Triggering GPTM1 with GPTM0 Update Event

Rev. 1.10
33 34
FA FB
14 15 00
FA
Software clearing
247 of 590
35 36
FC
Software clearing
01 02
FB FC
November 28, 2018
00 01
FD
03
FD