Holtek HT32F12345 User Manual page 356

32-Bit Arm ® Cortex ® -M3 MCU
HT32F12345
Bits Field
[6] CH2OCF
[5] CH1OCF
[4] CH0OCF
[3] CH3CCIF
[2] CH2CCIF
[1] CH1CCIF
Rev. 1.10
Descriptions
Channel 2 Over-capture Flag
This flag is set by hardware and cleared by software.
0: No over-capture event is detected
1: Capture event occurs again when the CH2CCIF bit is already set and it is not
cleared yet by software
Channel 1 Over-capture Flag
This flag is set by hardware and cleared by software.
0: No over-capture event is detected
1: Capture event occurs again when the CH1CCIF bit is already set and it is not
cleared yet by software
Channel 0 Over-capture Flag
This flag is set by hardware and cleared by software.
0: No over-capture event is detected
1: Capture event occurs again when the CH0CCIFbit is already set and it is not
yet cleared by software
Channel 3 Capture / Compare Interrupt Flag
- Channel 3 is configured as an output
0: No match event occurred
1: The contents of the counter CNTR have matched the contents of the CH3CCR
register.
This flag is set by hardware when the counter value matches the CH3CCR value
with exception in the center-aligned counting mode. It is cleared by software.
- Channel 3 is configured as an input
0: No input capture occurred
1: Input capture occurred
This bit is set by hardware when a capture event occurs. It is cleared by software or
by reading the CH3CCR register.
Channel 2 Capture / Compare Interrupt Flag
- Channel 2 is configured as an output
0: No match event occurred
1: The contents of the counter CNTR have matched the contents of the CH2CCR
register
This flag is set by hardware when the counter value matches the CH2CCR value
with exception in the center-aligned counting mode. It is cleared by software.
- Channel 2 is configured as an input
0: No input capture occurred
1: Input capture occurred.
This bit is set by hardware on a capture event. It is cleared by software or by reading
the CH2CCR register.
Channel 1 Capture / Compare Interrupt Flag
- Channel 1 is configured as an output
0: No match event occurred
1: The contents of the counter CNTR have matched the contents of the CH1CCR
register
This flag is set by hardware when the counter value matches the CH1CCR value
with exception in the center-aligned counting mode. It is cleared by software.
- Channel 1 is configured as an input
0: No input capture occurred
1: Input capture occurred
This bit is set by hardware on a capture event. It is cleared by software or by reading
the CH1CCR register.
356 of 590 November 28, 2018