32-Bit Arm
®
Cortex
®
-M3 MCU
HT32F12345
Frequency of the PLL output clock can be determined by the following formula:
Where NR = Ref divider = 2, NF1 = Feedback Divider 1 = 4, NF2 = Feedback Divider 2 = 1 ~ 16,
NO1 = Output Divider 1 = 2, NO2 = Output Divider 2 = 1, 2, 4, or 8.
Considering the duty cycle with 50 %, both input frequency and output frequency is divided by
2. Assume that a given CLK
frequency; it is recommended to load a larger value into the NF2 field to increase the PLL stability
and reduce the jitter with the expense of the settling time. The output and feedback divider 2 value
are described in Table 15 and Table 16. All the configuration bits (S1 ~ S0, B3 ~ B0) in Table 17
and Table 18 are defined in the PLL Configuration Register (PLLCFGR) and PLL Control Register
(PLLCR) in the section of Register Definition. Note that VCO
MHz. If your configurations exceed this range, the output frequency of USB PLL will not be
promised to match the above PLL
The USB PLL can be switched on or off by using the USBPLLEN bit in the Global Clock Control
Register (GCCR). The USBPLLRDY flag in the Global Clock Status Register (GCSR) will indicate
if the USB PLL clock is stable. An interrupt can be generated if the related interrupt enable bit
USBPLLRDYIE in the Global Clock Interrupt Register (GCIR) is set as the USB PLL becomes
stable.
Table 17. USB PLL Output Divider 2 Value Mapping
Output divider 2 setting S1 ~ S0 (USBPOTD)
Table 18. USB PLL Feedback Divider 2 Value Mapping
Feedback divider 2 setting B3 ~B0 (USBPFBD)
Rev. 1.10
NF
NF
1
2
PLL
CLK
OUT
IN
NR
NO
NO
1
frequency as USB PLL input generates a specific USB PLL output
IN
formula.
OUT
00
01
10
11
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
......
1111
89 of 590
NF
4
2
CLK
CLK
IN
IN
NO
2
2
2
2
is ranged from 48 MHz to 96
OUT
NO2 (Output divider 2 value)
NF2 (Feedback divider 2 value)
NF
2
NO
2
1
2
4
8
16
1
2
3
4
5
6
7
8
9
10
11
12
......
15
November 28, 2018
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