Holtek HT32F12345 User Manual page 274

32-Bit Arm ® Cortex ® -M3 MCU
HT32F12345
Bits Field
[3] CH3CCG
[2] CH2CCG
[1] CH1CCG
[0] CH0CCG
Rev. 1.10
Descriptions
Channel 3 Capture / Compare Generation
0: No action
1: Capture / Compare event is generated on channel 3
A Channel 3 Capture / Compare event can be generated by setting this bit. It is
cleared by hardware automatically.
If Channel 3 is configured as an input, the counter value is captured into the
CH3CCR register and then the CH3CCIF bit is set. If Channel 3 is configured as an
output, the CH3CCIF bit is set.
Channel 2 Capture / Compare Generation
0: No action
1: Capture / Compare event is generated on channel 2
A Channel 2 Capture / Compare event can be generated by setting this bit. It is
cleared by hardware automatically.
If Channel 2 is configured as an input, the counter value is captured into the
CH2CCR register and then the CH2CCIF bit is set. If Channel 2 is configured as an
output, the CH2CCIF bit is set.
Channel 1 Capture / Compare Generation
0: No action
1: Capture / Compare event is generated on channel 1
A Channel 1 Capture / Compare event can be generated by setting this bit. It is
cleared by hardware automatically.
If Channel 1 is configured as an input, the counter value is captured into the
CH1CCR register and then the CH1CCIF bit is set. If Channel 1 is configured as an
output, the CH1CCIF bit is set.
Channel 0 Capture / Compare Generation
0: No action
1: Capture / Compare event is generated on channel 0
A Channel 0 Capture / Compare event can be generated by setting this bit. It is
cleared by hardware automatically.
If Channel 0 is configured as an input, the counter value is captured into the
CH0CCR register and then the CH0CCIF bit is set. If Channel 0 is configured as an
output, the CH0CCIF bit is set.
274 of 590 November 28, 2018