Holtek HT32F12345 User Manual page 11

32-Bit Arm ® Cortex ® -M3 MCU
HT32F12345
Register Map ..................................................................................................................... 368
Register Descriptions ......................................................................................................... 369
RTC Counter Register - RTCCNT ................................................................................................ 369
RTC Compare Register - RTCCMP ............................................................................................. 370
RTC Control Register - RTCCR ................................................................................................... 371
RTC Status Register - RTCSR..................................................................................................... 373
RTC Interrupt and Wakeup Enable Register - RTCIWEN ............................................................ 374
18 Watchdog Timer (WDT) .................................................................................... 375
Introduction ........................................................................................................................ 375
Features ............................................................................................................................. 375
Functional Description ....................................................................................................... 376
Register Map ..................................................................................................................... 377
Register Descriptions ......................................................................................................... 378
Watchdog Timer Control Register - WDTCR ............................................................................... 378
Watchdog Timer Mode Register 0 - WDTMR0............................................................................. 379
Watchdog Timer Mode Register 1 - WDTMR1............................................................................. 380
Watchdog Timer Status Register - WDTSR ................................................................................. 381
Watchdog Timer Protection Register - WDTPR ........................................................................... 382
Watchdog Timer Clock Selection Register - WDTCSR ................................................................ 383
19 Inter-Integrated Circuit (I
Introduction ........................................................................................................................ 384
Features ............................................................................................................................. 385
Functional Descriptions ..................................................................................................... 385
Two Wire Serial Interface .............................................................................................................. 385
START and STOP Conditions ....................................................................................................... 385
Data Validity .................................................................................................................................. 386
Addressing Format ....................................................................................................................... 386
7-bits Address Format ................................................................................................................... 386
10-bits Address Format ................................................................................................................. 387
Data Transfer and Acknowledge ................................................................................................... 388
Clock Synchronization .................................................................................................................. 389
Arbitration ..................................................................................................................................... 389
General Call Address .................................................................................................................... 390
Bus Error ....................................................................................................................................... 390
Address Mask Enable ................................................................................................................... 390
Address Snoop ............................................................................................................................. 390
Operation Mode ............................................................................................................................ 390
Conditions of Holding SCL Line .................................................................................................... 395
I 2 C Timeout Function .................................................................................................................... 396
PDMA Interface ............................................................................................................................. 396
Rev. 1.10
C) ............................................................................ 384
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11 of 590 November 28, 2018